Integration of low-k materials as a sidewall spacer is a key challenge for smaller technology nodes. For example, a profound fail mode is associated with low-k spacer damage which occurs from post poly pull cleaning processes in replacement gate processes. In this fail mode, the low-k erosion at the top part of gate results in a taper profile that heavily degrades metal gate height variability, while hurting the short margin between the source/drain contact and the gate metal. In essence, this fail mode has prevented implementation of lower-k spacer to further boost device performance.